...
| Power Limits | OS Setings | Single core | Multi core | Vulkan | OpenCL | llvmpipe |
|---|---|---|---|---|---|---|
| 15/15 | powersave | 1288 | 3278 | 3899 | 4279 | |
| 15/15 | balance_performance | 1289 | 3292 | 3911 | 4293 | 330 |
| 15/15 | performance | 1291 | 3196 | 4015 | 3647 | 335 |
24.04 to 25.04
/proc/cpuinfo diff
| Code Block |
|---|
flags : ..., pcid, ...
d. Process Context IDentifiers (PCID) is a CPU feature that
allows us to skip flushing the entire TLB when switching page
tables by setting a special bit in CR3 when the page tables
are changed. This makes switching the page tables (at context
switch, or kernel entry/exit) cheaper. But, on systems with
PCID support, the context switch code must flush both the user
and kernel entries out of the TLB. The user PCID TLB flush is
deferred until the exit to userspace, minimizing the cost.
See intel.com/sdm for the gory PCID/INVPCID details. |
dmidecode diff
| Code Block |
|---|
root@server5:/storage/backup/server5# diff dmidecode.txt dmidecode-2504-1.txt
1c1
< # dmidecode 3.5
---
> # dmidecode 3.6
4,5d3
< # SMBIOS implementations newer than version 3.5.0 are not
< # fully supported by this version of dmidecode.
128c126,127
< Type: 32-bit PCI Express x1
---
> Type: PCI Express x1
> Data Bus Width: 32 bit
140c139,140
< Type: 32-bit PCI Express x1
---
> Type: PCI Express x1
> Data Bus Width: 32 bit
152c152,153
< Type: 32-bit PCI Express x1
---
> Type: PCI Express x1
> Data Bus Width: 32 bit
164c165,166
< Type: 32-bit PCI Express x1
---
> Type: PCI Express x1
> Data Bus Width: 32 bit
176c178,179
< Type: 32-bit PCI Express x1
---
> Type: PCI Express x1
> Data Bus Width: 32 bit
1359c1362
< DB 6A 7C 00 01 04 01 55 02 00 90 06 01 10 8B 20
---
> DB 6A 7C 00 01 04 01 55 02 00 90 06 01 10 80 20
|